Assalamu alaikum,
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We have an open position for SRAM Devices Technologist located in New York, US. This position is visa sponsor / transfer eligible. Any Pakistanis currently located in US with relevant skill set? Feel free to shoot over your resumes to me. Please spread the word.
See the job description below.
Introduction
This position will be responsible for working on high density SRAM memory in state-of-the-art CMOS logic process technologies. The incumbent will both develop and integrate high density SRAM devices into the current Logic process flows, optimized for performance, reliability, device mismatch, yield and ease of manufacturing.
Responsibilities
* Responsible for all aspects of the SRAM module development including structural development of SRAM bit cells, SRAM device development, integration into baseline processes, characterization of the cells, and analysis of parametric data bridging into yield engineering activity.
* Design, execute, and analyze experiments aimed at the creation and optimization of leading-edge silicon transistor technology (20nm technology generation and beyond) within a development environment. This will include both physical and electrical data analysis, as well as extensive coordination with the joint technology development alliance integration, device, and unit process module groups.
* SRAM cell device design and performance optimization across different cells.
* Mismatch(Avt) improvement plan and execution to meet technology Vmin requirement for low leakage and performance SRAM cell families at a given technology.
* Silicon HW learning planning and execution as well as electrical data analysis.
Requirements
* Minimum Masters Degree with 5+ - 7 years of experience in device module development and SRAM process integration knowledge or related experience with a similar skill set.
* Ph.D. highly preferred but not required.
* A thorough knowledge of SRAM functional operation, CMOS device physics, state-of-the-art CMOS logic process technologies, and logic process integration is preferred.
* Ability to aggressively execute complex process/device experiments and focus on solving problems individually or as part of a team is desirable.
* Experience with scribe test structure layout( testing macros), parametric program setup, and bench measurements and familiarity of electrical characterization is a plus.
* Strong fundamental understanding of solid state device physics, sub-0.1-micron FET architectures, and the implications of device characteristics and performance on technology and product behavior.
* Fundamental understanding of unit process and module interactions (including all FEoL unit processes, such as shallow trench formation, fill and CMP, gate dielectric and electrode formation, implant and implant masking and activation, and gate spacer and silicide contact formation) on electrical parametric, product yield, and performance behavior.
* Direct experience in low-leakage / low-power device design and optimization is strongly desired, and additional technical experience in FEOL reliability, defect inspection and reduction, yield analysis, and/or test structure design is a plus.
Adnan Tariq
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