Dear Habeeb,
Please write me directly what information you need (nazar.abbas@seecs.edu.pk). In brief, it is a USB3.0 IP Core suite comprising of USB3.0 host and device controllers. The IP cores are currently made for FPGAs and tested/verified through 3rd party tools.
We have added an Event Driven Power Management Control which monitors all the ongoing activities and switches those modules ON related to a particular transaction. That is an additional module to those power saving modes provided in USB3.0 Specifications (U0, U1 , U2).
with regards
--Nazar
On Wed, Sep 21, 2011 at 3:18 AM, Habeeb Quazi <habeeb2083@yahoo.com> wrote:
Good work!Is there more information on this?I am looking to see what kind of low power techniques were used.Has this been synthesised for ASIC rather than just FPGA? Because with the smartphone/tablet boom this could be an ideal solution as we see USB 3.0 devices emerging.
From: shehryarshaheen <shehryar.shaheen@gmail.com>
To: pakgrid@yahoogroups.com
Sent: Tuesday, 20 September 2011, 11:46
Subject: [pakgrid] Re: USB 3.0 IP core developed in PakistanCongratulations, this looks great
Here is some input that can add value to your development effort.
After getting the USB 3.0 digital cores (Host/Device) done, additionally if you can also put in some effort towards creating the PHYs for USB 3.0 , that will add value to your development effort and the product offering can become more complete.
I've seen that the licensing costs for PHYs actually exceeds the costs of the Digital core and having a Digital core + PHY solution makes your product that much more complete and it will also will fetch a bigger price.
I'm sure that a lot of verification effort has gone into verifying these cores, from an end user perspective customers will quite often ask for test plans and coverage reports. As this is how the Quality of the verification effort is established by the end user. So along with the User Guides and Data sheets some effort into putting together an End user consumable test plan along with coverage reports (that can be reproduced at the user site) will also add value.
Yet another thing would be to look into using FPGA internal transceivers as USB 3.0 phys. The Xilinx Virtex series FPGAs have internal transceivers collectively called RocketIO ( these the GTP/GTX/GTH transceivers )
These transceivers can be configured to act as PHYs for PCI Express , SATA and also USB 3.0 ( PCIe Gen 2 PHY and USB 3.0 PHY are very similar , in fact they are grouped under the same spec ).
Having an FPGA internal PHY option will mean that the board's BOM ( Bill of Materials ) is reduced which is something that all end users are looking for.
Congrtulations once more and best of luck for future efforts.
--- In pakgrid@yahoogroups.com, adeel asif <adeel_raja84@...> wrote:
>
> Salam All,
> ����������� Please have a look at this video to make you feel proud of what can be done in Pakistan.
>
>
> http://www.youtube.com/watch?v=dWyAYuIvwt0
>
> Regards,
> Adeel
>
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