Dear Sheharyar,
Salam,
We thank for your time and very valueable comments on the developed USB3.0 IP Core Suite at SEECS NUST Pakistan. The project is financially backed by National ICT R&D Fund Islamabad. Thanks for their efforts and support for us. We are now entering its marketing phase and looking foward for serious business partaners to work with them.
Your input is very welcomed.
you wrote:
After getting the USB 3.0 digital cores (Host/Device) done, additionally if you can also put in some effort towards creating the PHYs for USB 3.0 , that will add value to your development effort and the product offering can become more complete.
I've seen that the licensing costs for PHYs actually exceeds the costs of the Digital core and having a Digital core + PHY solution makes your product that much more complete and it will also will fetch a bigger price.
No doubt, creating PHYs for USB3.0 will add value to our product. Currently we are using 3rd party USB3.0 PHYs for our host and device but for our test model to provide an acceptable test plan and coverage reports to end users. We will be now exploring the opportunities to develop our own USB3.0 PHY solutions or inviting 3rd parties to work with us.
You wrote:
I'm sure that a lot of verification effort has gone into verifying these cores, from an end user perspective customers will quite often ask for test plans and coverage reports. As this is how the Quality of the verification effort is established by the end user. So along with the User Guides and Data sheets some effort into putting together an End user consumable test plan along with coverage reports (that can be reproduced at the user site) will also add value.
Yet another thing would be to look into using FPGA internal transceivers as USB 3.0 phys. The Xilinx Virtex series FPGAs have internal transceivers collectively called RocketIO ( these the GTP/GTX/GTH transceivers )
Just to save our time we purchased 3rd party FPGA boards with builit-in USB3.0 PHYs and that worked well. I still believe that your suggestion is very valid and it is a feasible solution. I think we will be exploring your proposed solution as well.
Best regards
-- Nazar
Congratulations, this looks great
Here is some input that can add value to your development effort.
After getting the USB 3.0 digital cores (Host/Device) done, additionally if you can also put in some effort towards creating the PHYs for USB 3.0 , that will add value to your development effort and the product offering can become more complete.
I've seen that the licensing costs for PHYs actually exceeds the costs of the Digital core and having a Digital core + PHY solution makes your product that much more complete and it will also will fetch a bigger price.
I'm sure that a lot of verification effort has gone into verifying these cores, from an end user perspective customers will quite often ask for test plans and coverage reports. As this is how the Quality of the verification effort is established by the end user. So along with the User Guides and Data sheets some effort into putting together an End user consumable test plan along with coverage reports (that can be reproduced at the user site) will also add value.
Yet another thing would be to look into using FPGA internal transceivers as USB 3.0 phys. The Xilinx Virtex series FPGAs have internal transceivers collectively called RocketIO ( these the GTP/GTX/GTH transceivers )
These transceivers can be configured to act as PHYs for PCI Express , SATA and also USB 3.0 ( PCIe Gen 2 PHY and USB 3.0 PHY are very similar , in fact they are grouped under the same spec ).
Having an FPGA internal PHY option will mean that the board's BOM ( Bill of Materials ) is reduced which is something that all end users are looking for.
Congrtulations once more and best of luck for future efforts.
--- In pakgrid@yahoogroups.com, adeel asif <adeel_raja84@...> wrote:
>
> Salam All,
> ����������� Please have a look at this video to make you feel proud of what can be done in Pakistan.
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